Aurasemi – Timing (AU5508) (10/2023)
The AU5508 offers most integrated 5G clock solution: Combines BBU, Wireline, AAU, Serdes requirements in one part definition.
- Unique integration of Sync Features
- Enables Systems with Low Constant Time Interval Error
- IEEE1588/SyncE/1 PPS full support
- Lower jitter for higher data rate links
- Lower close in noise and JESD204B/C full support for AAU RF clocks
- Integrated feature rich single part offers unparalleled flexibility to the system designer
Features:
- Ultra Performance PLLs
- Fully Integrated design with no external components
- 120 fs Typical RMS integrated jitter (12k-20M)
- 122.88M Output with excellent close in noise performance
- Fully Flexible Output and Input Mux: High level of flexibility in output allocation for PLLs
- JESD204B/C Support for data converter clocks
- 1 PPS Input / Output Support with sub 20s lock time
- External EEPROM Support
- TDC Mode available on all input clocks to measure input delays with < 10 ps accuracy: 10 TDC Channels available (independent of the PLLs)
- Frequency Control DCO: DCO Control on all outputs (down to 1/16 ppt)
- Phase Control DCO: Fine phase adjustment knob for phase of all outputs from a PLL (adjustment accuracy < 1ps) in both closed loop and open loop modes
- Internal modes to combine wander of OCXO with jitter of XO for holdover– Provides 24 hour holdover with programmable HO accuracy settings
- Best in class hitless switching performance: PBO with sub 25 ps hit, Phase Propagation & Frequency Ramp with programmable freq/phase slopes
- Fully integrated Jitter and wander attenuation options down to 0.09 mHz
- Repeatable input to output delays with output relative delay adjust
- Internal ZDB Mode with < 0.5 ns Input to Output delay independently available for each PLL
- Outputs can be phase aligned an independent sync pulse
- 72 QFN 10mm X 10mm Package